Atlas SCT Test DAQ Online Documentation

Lars Eklund , John Hill , Gareth Moorhead and Peter Phillips

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Configuration: System    Modules    BurstTypes    TriggerTypes    VariableTypes    ChipParams    AnalogueScans    DigitalScans   
CERN    Atlas    SCT    TestDAQ    RAL    Cambridge    Melbourne    UCL   

Contents

General Introduction
SCTDAQ is a software package which has evolved for testing SCT hybrids and modules at the testbeam, systemtest, PS irradiations, and many institute labs. It runs on a Windows PC which is connected to one or more VME crates via National Instruments VME-VXI interfaces. It consists of a compiled Dynamic Link Library (DLL) and a set of
ROOT macros. ROOT is an analysis environment developed at CERN as a modern successor to PAW, providing histogramming, script execution etc. in C++. The user environment consists of a great many scripts for performing specific tests or configuration tasks, on an individual module or multi-module system-wide basis; most of these scripts are executed from very simple menu bars which appear when the main macro script is executed.

SCTDAQ uses the testing DAQ hardware developed at RAL, Cambridge and UCL to provide for near-term, convenient testing of hybrids and modules. These are VME modules: the MuSTARD for readout, the SLOG for long configuration commands and general clock and command fan-out, and the CLOAC for system-wide clock and fast trigger and reset commands. In addition, SCTDAQ uses the prototype SCT low voltage and high voltage supplies, SCTLV and SCTHV, to provide hybrid power, slow control and detector bias. Links to the hardware writeups will be found at the top of this page.

For the majority of laboratory module testing and characterisation, electrical readout of the modules is used. The ABCD readout chips on the module hybrids, and the Mustard and Slog, all use the LVDS differential-pair electrical communication standard for the fast signals which are clocked at 40MHz. For electrical testing, the LVDS signals from the detector modules are generally buffered using repeater chips on a "support card", which also provides a more convenient and robust cable termination than does the module.

Details on the installation of the main VME modules and their use for electrical testing of detector modules can be found in the installation notes .

Another important application is in the testing of modules with optical links as will be used by SCT in ATLAS. This has been primarily done at the SCT Systemtest at CERN, and SCTDAQ includes software support for the optical interface modules which come between the modules and Mustard and Slog, BiLED and OPTIF. Support is also provided for temperature measurement modules which may be present.

SCTDAQ is also used, with specialised extensions, for the SCT Testbeams at CERN and KEK, and also for module performance monitoring during proton irradiation at the CERN PS.


Starting Up
To start the system, ensure that the modules are cabled as required, that the
configuration files reflect the physical reality, and then power on your VME crate.

Start ROOT, usually by clicking on a ROOT desktop icon. At the ROOT prompt, execute the main SCTDAQ macro by doing ".X ST.cpp". This is historic: "ST" because the program started life in the CERN SCT Systemtest.

ROOT will begin to execute the ST.cpp script, endeavouring to initialise hardware and software in various stages. Keep an eye out for any error messages: the scroll-back feature of the text window under Windows NT (but not 98) can be useful for this.

The system will first establish if it is necessary to run the NI-VXI Resource Manager and do so if required. Next the software will endeavour to "map" all VME modules, which should succeed if their addresses have been set correctly. It will then attempt to initialise the VME modules into known starting states.

The system will then read the configuration files, firstly for the system as a whole, and then for individual detector modules. Shortly after this, the SCTLV channels configured for each installed detector module will be powered on, as indicated by a green LED above the power connector on SCTLV2 or 3 (but not LV1). At this point the detector modules should respond on their data links with a "Clock Through", a 20MHz signal indicating that the master chips are alive and receiving a clock, and that the uplink data circuit is working. You can monitor the data link signals on an oscilloscope: for the first data link of the first module, this is usually the Lemo output labelled "MA" on the Mustard front panel. See the Mustard documentation for more details. The 20MHz signal should be present only for a few seconds, as shortly afterwards the system will attempt to configure the modules into a default state. If this configuration is successfull, the 20MHz signal will disappear.

At this point, the detector modules should be ready to receive triggers or more configuration commands, i.e., ready to take data. Your PC should also be displaying three windows:

When first getting started, useful options are: The system should now be ready for detailed module testing. The menu options will create further sub-menu windows and more histogram displays as needed. You can also enter commands at the interactive "Rint" window, or write macros. Generally, the system is designed to be extremely flexible and extensible.


Software Configuration
There are several important configuration files normally residing in the directory d:\sctvar\config. Note this is different to c:\sctdaq\config which contains examples which are not used. We use the "d:\" directory so that the detailed local configurations are not over-written every time the software is upgraded. All the configuration files are simple text files which can be edited with Notepad, Emacs or any other text editor.

Please note that changes have been made to the configuration functionality to make life easier during production testing. If you are not already familiar with these changes, please read this section carefully.

The most important file is d:\sctvar\config\st_system_config.dat.

This file contains some lines of descriptive comment, followed by a list of settings, one per installed detector module. This might look like:

       DETECTOR  LV     HV     SLOG      RSLOG    OPTO_TX        ROPTO_TX   OPT0_RX          MuSTARD          Module          Device Type
       id pr ac  cr ch  id ch  id ch pg  id ch pg typ id ch iset typ id ch  id c0 c1 tr0 tr1 id s0 s1 d0 d1   Filename        (optional)
-------------------------------------------------------------------------------------------------------------------------------------------
Module  0  1  1   0  0   0  0  0  0  0   0  1  0   -1 -1  1  0    -1 -1  2  -1  0  1 100 100  0  0  1 20 20   20220170100019  Barrel_Module
Module  1  1  1   0  1   0  1  0  2  0   0  3  0   -1 -1  2  0    -1 -1  3  -1  2  3 100 100  0  2  3 20 20   20220170100028  Barrel_Module
Module  2  1  1   0  2   0  2  0  4  0   0  5  0   -1 -1  3  0    -1 -1  4  -1  4  5 100 100  0  4  5 20 20   20220170100042  Barrel_Module
#Module  3  0  1   0  3   0  3  0  6  0   0  7  0   -1 -1 -1  0    -1 -1 -1  -1  6  7 100 100  0  6  7 15 15   20220170100034  Barrel_Module
In this example, there are three modules present, with serial numbers 20220170100019, ..28 and ..42. (The "#" character has been used to comment out the system configuration entry for Module ..34.)

The "DETECTOR" columns are:

Most of the remaining columns indicate to the software which of the available VME module channels are being used for that detector module. E.g., for "LV" we indicate a Crate and Channel number. For Mustard we indicate a Mustard identifier, "id", indicating which of potentially several Mustards, as well as the two active data "streams", "s0" and "s1", as well as certain channel-specific delay settings, "d0" and "d1". Each VME module has its own requirements, and many are specific to optical readout.

The penultimate column (which is the final required field) gives each module a name. In the traditional mode of operation of SCTDAQ, this string is used to identify the module-specific configuration file to be used. Such files are named according to the convention "d:\sctvar\config\NAME.det", hence for the example system configuration shown above the system would expect to find files named 20220170100019.det, 20220170100028.det and 20220170100042.det.

The final column, which can be omitted if desired, may be used to record the type of device connected to each test station. This information is placed into the results files for future reference, but is otherwise ignored. Typical hybrid/module types include the following:

With the above configuration scheme, a large number of essentially identical files would need to be generated during the production phase of our experiment. This seems rather unnecessary, hence two alternatives have been developed. These options are described below.

If a module specific configuration file "NAME.det" cannot be found, the software will look for a default detector configuration file, "default.det". If this is found, its contents are used to set the parameter values of module "NAME". (If the default file cannot be found, or the file is not interpreted correctly, the module corresponding module is marked "Absent". It can hence be seen that the original behaviour of SCTDAQ with regard to missing detector configuration files is maintained as long as the default file is missing. )

A further possibility is for the user to edit the system configuration file to specify that the default detector configuration file is to be used for each module. Under such circumstances the user will be prompted at system startup to enter the serial number of each of the modules connected to the system, and to select an appropriate device type from a short list of options. It is envisaged that most production test sites will find this to be the most convenient mode of operation.

An updated example of a default detector configuration file for a module with ABCD3T chips is given in the file "c:\sctdaq\config\default.det". This is reproduced below.

#
# Default Configuration file for ABCD3T module
#
# P.W.Phillips 18.01.2002
#
# Here is a brief explanation of the variables that have to be set:
#
# First row
#  Required for all modules
#   Link0   enable MUSTARD channel 0 (associated to first hybrid)
#   Link1   enable MUSTARD channel 1 (associated to second hybrid)
#   Oddity  How is the top address line of the chips bonded?
#            -1 - follows SELECT line
#             0 - bonded low => hybrid is even
#             1 - unbonded   => hybrid is odd
#   Chipset 3 = ABCD (not actually used yet)
#   DTM     "Enable Data Taking Mode" - set 1 here!!
#  Extras required for Liverpool Forward Support Card
#   (see http://hep.ph.liv.ac.uk/~ashley/support.html)
#   SCmode  Support Card readout mode (0-3)
#   bpm_dr  DORIC bpm drive current (0-4)
#   vdac0   threshold for data receiver 0 (0-1023)
#   vdac1   threshold for data receiver 1 (0-1023)
#
# Second row
#  Required for all modules
#   Select use primary or redundant clock and control
#   Vdet    detector bias voltage
#   Idet    detector bias current trip limit (remember to allow for charging currents)
#   Vcc
#   Icc     current warning limit (no effect)
#   Vdd
#   Idd     current warning limit (no effect)
#   Vi1     - redundant -
#   iVi1    - redundant -
#   vled0   (Vvcsel0)
#   Iled0   (Ivcsel0) current warning limit (no effect)
#   vled0   (Vvcsel0)
#   Iled0   (Ivcsel0) current warning limit (no effect)
#   Vpin
#   Ramp    HV ramp rate [1(fast) - 4(slow)] (assumes SCTHV)
#
# One row per chip, preceeded by "Chip n" tag
#  Comp.    Compression mode (0-3)
#  Act.     Is chip active? (must be active to participate in scans)
#  Cal_m    Calibration Mode - select strobed cal line (0-3)
#  T_range  TrimDAC range (0-3)
#  Mask_r   Mask bit - readout contents of mask register (0/1)
#  Edge     Edge Detect bit (0/1)
#  Acc.     Accumulate bit (0/1)
#  Del.     Strobe Delay      (0-63)
#  Vth      Threshold Voltage (0-637.5 mV)
#  Vcal     Calibration level (0-159.375 mV)
#  FEShp.   FE Shaper Current (0-37.2 microA)
#  FEBias   FE Bias Current   (0-285.2 microA)
#  Role     Role of chip:
#             0 - missing
#             1 - dead    (bypass this chip)
#             2 - end
#             3 - master
#             4 - slave
#             5 - lonely  (master + end)
#
#
Module : Link0  Link1  Oddity Chipset DTM SCmode bpm_dr vdac0 vdac1
           1      1      -1      4     1    0      3     512   512
	 Select  Vdet  Idet  Vcc  Icc  Vdd  Idd  Vi1  iVi1 Vled0 Iled0 Vled1 Iled1 Vpin Ramp
	    0    200.  100.  3.5 1000. 4.0  600.  0.  10.    6.   10.    6.   10.   6.   4

Chip 0 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   38   500. 15. 30.0   220.0     3  
Chip 1 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   38   500. 15. 30.0   220.0     4  
Chip 2 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   38   500. 15. 30.0   220.0     4  
Chip 3 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   38   500. 15. 30.0   220.0     4  
Chip 4 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   38   500. 15. 30.0   220.0     4  
Chip 5 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   38   500. 15. 30.0   220.0     2  
Chip 6 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   40   500. 15. 30.0   220.0     3  
Chip 7 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   40   500. 15. 30.0   220.0     4  
Chip 8 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   40   500. 15. 30.0   220.0     4  
Chip 9 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   40   500. 15. 30.0   220.0     4  
Chip 10: Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   40   500. 15. 30.0   220.0     4  
Chip 11: Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
           1     1     0     0     0    0    0   40   500. 15. 30.0   220.0     2  
#
# optional extensions
#
# list of masked channels, preceeded by tag "Mask"
#
# 1536* TrimDAC settings (integers), preceeded by tag "Trim"
#
Further explanation of some of these parameters: Additional files which are used if present include:

suggestions/corrections