-------

ATLAS SCT

Proposed Hybrid / Module Electrical Test Procedures

This is a PROPOSAL for guidelines to be advertised by the TestDAQ group for use in the immediate future, not necessarily longer-term or production testing : please comment

Why use common chip settings & optimisation rules ?

  • Comparison of results different modules and/or test systems
  • Help new groups
  • Design test systems & software

Optimisation

  • Operating modes (throughout):
    • Edge Detection ON (more aggressive)
    • Compression mode: Anyhit ( or 01X - shouldn't matter with edge detection on)
  • Strobe Delay Optimisation & Delay Calibration:
    • At nominal FE Bias and Shaper settings (e.g., ABCD1: FEB 202uA, FESh 18uA)
    • Strobe delay scan (Occupancy vs Strobe delay) at Qi 4fC, threshold 200mV
    • -> optimum setting; delay calibration (PLOT)
  • FE Bias & Shaper Optimisation:
    • 9 points at and around (+/- 1 unit) nominal FE Bias & Shaper
      (more points if necessary)
    • "Quick" threshold scans at two Qi settings: 2.5, 3.5fC (Vcal 25, 35mV)
      100-500mV, 25 steps, at least 100 events /step
    • Extract VT50 and output noise from S-curve fits for each channel (PLOT)
    • Simple linear fit -> Gain slope and offset for each channel (PLOT)
    • Use Gain and Output noise at 2.5fC to extract Input Noise (ENC) (PLOT)
    • Histogram offset spread and ENC for each chip (PLOT)
    • Choose optimal FE Bias and Shaper setting for each chip

Calibration & Noise Measurement

  • At optimal Strobe delay, FE Bias & Shaper for each chip
  • Detailed threshold scans at many Qi settings: (1.5),2.0,2.5,3.0,3.5,4.0,(4.5,5.0)
    100 to 500 mV threshold in 25 steps, at least 100 events /step (more if faster system)
  • Extract VT50 and output noise from S-curve fits for each channel (PLOT)
  • Linear fit of "selected linear region" -> Gain extrapolated to 1.0fC for each channel (PLOT)
  • Use Gain and output noise (at lowest Qi with reasonable S-curves) to extract Input Noise (ENC) (PLOT)

Gareth.Moorhead@cern.ch