Draft 3.1
This update owes much to the efforts of Peter Phillips
(electronics sections) and Dave Robinson (detector sections) in particular.
Testing procedures for SCT modules
Contents
1. Introduction
2. Testing sequence
2.1 Component tests
2.1.1 Introduction
2.1.2 Reception of parts
2.1.3 Hybrid tests
2.1.4 Detector tests
2.1.5 Fan in tests
2.2 Sub assembly tests
2.3 Module tests
2.4 Tests after shipping
3. Batch tests
3.1 Hybrids
3.2 Detectors
3.3 Detector test structures
4. Standard testing conditions
4.1 Chip tests
4.1.1 Check of hybrid supply currents
4.1.2 Hybrid temperature cycling
4.1.3 Burn in
4.1.4 Test vectors: Simple
4.1.5 Test vectors: Full
4.1.6 Test vectors: Data run
4.2 Detector tests
4.2.1 IV curves
4.2.2 CV curves
4.2.3 Strip integrity
4.2.4 Leakage current stability
4.2.5 Irradiation tests
4.2.6 Interstrip capacitance
4.2.7 Polysilicon and interstrip resistance
4.2.8 Coupling capacitance
4.3 Additional test structure tests
4.3.1 Metal series resistance
4.3.2 Polysilicon bias resistance
4.3.3 Sheet resistance of implants
4.3.4 Flat band voltage
4.4 Fan-in tests
5. Table of tests, variables and criteria
6. Infrastructure requirements
1. Introduction
This document is a 'living document', liable to be updated at any time.
It has grown initially from a series of presentations and discussions in
the CERN GENEVA cluster which were then presented in the June 98 SCT week.
Following the suggestions then given, each cluster rep. nominated a testing
representative. In its present form it owes more to the efforts of the
people who prepared QA documents in the UK and the many suggestions from
testing representatives in each cluster. These people (listed below) are
consulted before each release of the document, and continue to contribute
to the detailed procedures described here.
Testing reps:
-
Craig Buttar
-
Peter Ratoff
-
Tim Jones
-
Steve Snow
-
Pablo Modesto
-
Carl Haber
-
Gareth Moorhead
-
Laci Andricek
-
Steinar Stapnes
-
Dave Robinson
Suggestions should be sent to me, shaun.roe@cern.ch
After each preliminary circulation of the document to these people (and
absorbing their comments), it is posted here for wider comment by the sct
community.
The document is divided into six
parts:
1) An introduction
2) A section giving overall testing procedure seen as a sequence, with
cursory explanations of the tests and their aims. Web links to detailed
explanations of section 3.
3) Batch tests, to be performed on a subset associated
with production
4) Detailed specifications of the tests, with reference to other documents
where appropriate, and a description of the likely equipment and manpower
needed.
5) A list of variables extracted from the tests, with pass/fail criteria
where appropriate.
6) Infrastructure requirements
I should like this document, initially, to be as complete as possible
in terms of the possible tests to be performed. In actual production, and
with experience, it will become clear which of the tests are actually necessary
in terms of verifying the final production quality.
Despite the categorical tone, nothing is set in stone, everything
is up for discussion. In particular, in this initial stage, I would
welcome comments on the overall structure.
2.Testing sequence
I divide the testing into component(essentially hybrids and detectors),
sub-assembly (check on metrology), and module (final tests). In addition
to this sequence there is a section defining tests to be performed after
each transport of the module or hybrid, to ensure that no damage has occurred
in transit
2.1 Component tests
2.1.1 Introduction
I treat the hybrid and detectors separately and assume that the finished
pieces at the end of this stage are : Electrically tested hybrids with
chips on Tested detectors Inspected (tested?) additional mounting pieces,
including baseboard
These tests may be done partly or wholly in industry.
The parts list for each module type should be listed in section
3
2.1.2 Reception of parts
All parts are received and checked against an inventory; where appropriate,
manufacturers information is entered in the database.
The pieces are visually inspected for obvious defects.
Some parts (which ones?) may be mechanically measured on a batch basis
to ensure they are within tolerance.
2.1.3 Hybrid tests
1. The hybrid supply currents are checked at room temperature to ensure
they are within an acceptable range. (detail in section....)
2. The hybrids are cycled ten times from -20°C to 50°C (? to
be defined) while maintaining a constant check on the currents (detail
in section....)
3. The hybrids are subjected to a 100 hour burn-in at 20°C (?)
while checking the currents.
4. Full test vectors checking each chip are sent, and the reply read
back and checked for conformity
5. A data run (detail in ...) is performed on each hybrid at the end
of the burn-in to ascertain the overall dynamic functionality and individual
channel characteristics (gain, pedestal, noise)
2.1.4 Detector tests
1. IV characteristic up to 300 V
2.1.5 Fan-in tests
1. The fanins will be inspected optically for shorts
2. The fanins will be tested electrically
2.1.x other pieces...
2.2 Sub-assembly tests
1. Reception tests, as defined in 2.4
2. Leakage current of the glued detector assembly
3. Intermediate metrology, 26 points per module
(see http://wwwcn1.cern.ch/~sroe/equipment/test_hnd.pdf)
2.3 Module tests
1. Reception tests, as defined in section 2.4.
2. Detector IV
3. Detector I-time stability (in parallel with
6)
4. Cycle from +20 to -20 ten times, checking
currents
5. Check metrology and dynamic deformation
6. 100 hour burn in at the operating temperature,
checking currents
7. Data run at the operating temperature
8. Source or laser data run at operating temperature.
2.4 Tests after shipping of a hybrid or module
1. Visual inspection
2. Check supply currents
3. Supply simple test vectors to the chips, read
back the reply.
3. Batch tests
3.1 Hybrids
3.2 Detectors
Quantity
Initially 10%, reducing to 5% during production
Tests
1. Strip coupling oxide integrity, for all strips.
2. Time stability
3. Irradiation testing....(http://www.hep.phy.cam.ac.uk/silicon/detectortests.html)
4. Metrology of detectors on a vacuum chuck
Flatness and measurement of fiducials
3.3 Detector test structures
Quantity
Initially 10%, reducing to 5% during production
Tests
1. CV characteristics
2. Series resistance of strip metal
3. Resistance of polysilicon resistors
4. Sheet resistance of p and n implants
5. Flat band voltage from CV measurements of MOS
structures
4. Standard Testing Conditions
4.1 Chip tests on the hybrid or full module
4.1.1 Check of hybrid supply currents
Aim
Gross check of chip and hybrid functionality
Procedure
The currents should be checked, unless specified,
at room temperature with a current limited supply.
DACs should be at their nominal values. This
requires the hybrid to be clocked, reset, then configuration and DAC commands
to be sent.
The values are to be read 5 minutes after configuration
to allow the chips to warm up.
Acceptance criteria
For the ABCD:
|
Voltage [V] |
Nominal current |
Acceptable range |
Supply limit |
| Vdd |
4.0±0.1 |
40 mA per slave
50mA per master |
±20% |
600 mA |
| Vcc |
3.5±0.1 |
44 mA per chip |
±20% |
700 mA |
4.1.2 Hybrid temperature cycling
Aim
This test is intended to catch bad surface mount
soldering and microcracks.
Procedure
The hybrids are cycled from -20°C to 50°C
ten times while connected to their supply, temperature measured on the
hybrid ( Note: if the present hybrids are powered without any cooling,
they reach about 40°C at their hottest point)
A thermal image should be taken to demonstrate
that each chip is well coupled to the hybrid.
Acceptable current behaviour over this
range is yet to be ascertained.
4.1.3 Burn-in
Aim
Accelerated aging of the chips to catch infant mortality
Procedure
The hybrids are mounted into a test bench. The chips
are initialised and then clocked (40MHz) and triggered at 100kHz for the
duration of the test. The temperature on the hybrid is monitored, as are
the currents. The hybrids are maintained at 40°C for 100 hours.
Alarm conditions should be set on the temperature
and currents, so that the power is cut if necessary.
Acceptance
4.1.4 Test vectors specification: Simple
Aim
Gross check that each chip responds to a simple command
Procedure
Reset the hybrid/module and check that a 20MHz clock
is returned
Configure the hybrid /module in SendId mode
Send a L1 trigger: check that each chip responds
correctly
Acceptance
Every chip responds as predicted
4.1.5 Test vectors
specification: Full
Aim
Check that the chip responds to the full range of
commands
Procedure
1. Feedthrough test after reset
-
Reset the hybrid/module and check that a 20MHz clock
is returned
-
Check that the hybrid/module can be initialised by
either set of clock/command lines
2. SendId mode testss
-
load configuration register with different values
-
check chip address decoding
-
integrity of data redundancy connections (both sets
of token/data inputs/outputs);where appropriate, verify that bypassing
works
-
BC counter reset tests: sending BC counter reset
commeand + L1 trigger with several delays, comparing the BC counter value
in the output data, comparing the L1 counter value
3. Data taking mode, accumulator off, DCL hit mode
(00), mask bit on
-
No hit tests: rom 1 to 27 consecutive triggers
-
Single channel hit tests for: first channel hit;
last channel hit; random channel hits; (127 ch. masked)
-
First and last channels hit.(126 ch. masked)
-
All channels hit (no mask)
4. Data taking mode, front end disabled by setting
max. threshold, mask bit off
-
Accumulator on, DCL hit mode (00): no hit accumulator
test; all hits accumulator test (pulsing i/p register.
-
Accumulator off: testing all DCL modes (pulsing i/p
register, changing L1 trigger delay)
Acceptance
Every chip responds as predicted
4.1.6 Test vectors specification: Data run
Aim
Optimisation of chip parameters on a chip by chip
basis (e.g. strobe delay, bias and shaper currents), measurement of the
chip characteristics: gain, pedestal, noise
Procedure
To be defined, see:
http://www.cern.ch/Atlas/GROUPS/INNER_DETECTORS/SCT/testdaq/settings.html
Acceptance
Gains, pedestals and noise within acceptance criteria
(being defined); total number of bad channels within acceptance.
4.2 Detector tests
The detector specification document is at:
http://wwwcn.cern.ch/~allportp/specs.ps
This section has been substantially rewritten, following the procedures
described in Dave Robinsons document:
http://www.hep.phy.cam.ac.uk/silicon//detectortests.html
Tests should be carried out in a temperature (21±2°C)
and humidity (50% ±10%) controlled environment. Note that all probing
of detector pads should whenever possible use row C, as this is not used
ina ny stage of module construction.
4.2.1 IV Curves
Aim
IV measurement as check of detector quality, to cross-check
with manufacturer data and to ensure there has been no transit damage.
Procedure
The detector backplane is placed on the chuck of
a probestation and the IV characteristic between the bias rail and the
backplane measured using a computer controlled current meter and voltage
source. The detector bias may be applied via a front edge contact instead
of via the detector backplane if appropriate. The current is measured every
10V step up to 350V, with a 10 second delay between steps. The temperature
of the probestation environment should be recorded.
Acceptance
Detectors should display a characeristic which is
below 6µA at 150V and 20µA at 300V and 20deg C.
4.2.2 CV curves
Aim
To determine the depletion voltage and verify the
manufacturer data.
Procedure
Place the detector backplane on the chuck of a probestation
and contact the bias rail with a probeneedle. Measure the capacitance between
the bias rail and the backplane as a function of detector bias. Alternatively
the capacitance can be measured between the bias rail and the front edge
contact if appropriate. Record the capacitance in 10V steps up to 350V,
with a 10 second delay between steps. Use 1 kHz with CR in SERIES and level<0.5V.
Plot the data as 1/C**2 (1/nF**2) vs bias (volts), and extract the depletion
voltage.
Acceptance
Detector depletes below 150V
4.2.3 Strip integrity
Aim
Check each strip for punchthroughs to the oxide,
for shorts between strip metals, and for discontinuities in the strip metals
as a verification of manufacturer supplied data and to check that the strip
defects are within specifications.
Procedure
The detector is placed on the chuck of an automatic
probestation, and strip metal pads corresponding to Row C are probed under
computer control with the light on. Punchthroughs across the strip oxide
are determined by a measurement of current between the strip metal and
backplane with -100V on the needle and the detector backplane at ground
potential. A series resistor of ~2-5Mohm should be used to limit the current
in case of pinholes. The following technique for each strip measurement
has been demonstrated to work well without any damage to the detector,
and is therefore recommended, though alternative techniques are acceptable:
1.Connect the probeneedle to the voltage source
sourcing 0V and the backplane to ground using computer controlled switches
2.Step to strip n and raise the chuck
3.Increase the volt source to -10V, wait 1 second
and measure the current to determine electrical continuity across the oxide.
If there is electrical continuity (ie a pinhole exists at low volts) skip
steps 4 and 5 and go to step 6.
4.If there is no electrical continuity, increase
the volt source to -100V (no ramp), wait 1 second and recheck the electrical
continuity
5.Decrease the volt source to 0V (no ramp)
6.Switch the probeneedle to ground (ie short the
needle to the detector backplane) and wait for 500ms
7.Switch the probeneedle and backplane to the
CV meter
8.Wait 1 second and measure the CV (1kHz, CR in
SERIES)
9.Lower the chuck
10.Repeat the measurement cycle from point 1 above
for strip n+1.
The test (as demonstrated on a SUMMIT 10K probestation)
takes about 1 hour 10 minutes.
This may yet be modified: e.g. measure between
strip and bias rail, to try to catch bad resistor contacts as well
Component Acceptance
<2 % bad strips, where a bad strip is:
-
electrical continuity between the strip metal and
backplane
-
strip metal short to neighbour or evidence for metal
discontinuity
Batch acceptance
The batch is accepted if:
The mean number of good strips is 99% and no detector
falls below 98% good strips
4.2.4 Leakage current stability
Aim
To check that any variation in leakage current over
a 24 hour period is within specifications.
Procedure
Detector is assembled into a support frame and the
backplane and bias rail are bonded to soldable contacts. The assembly is
installed in an environment chamber containing dry air (nitrogen) maintained
at 20degC. The bias is ramped to 150V, and after 60 seconds settling time
the current is monitored every 15 minutes over a 24 hour period. Several
detectors may be measured in parallel by use of a switching matrix.
Acceptance
Maximum increase in leakage current during 24hours
is less than 2uA.
4.2.5 Irradiation tests
Aim
Establish the radiation hardness of detectors
Procedure
Detectors are measured as in 4.2.1 to 4.2.4, they
are then irradiated to 3 x 1014 n/cm2 equivalent
damage at -10°C in an inert atmosphere while under 150V bias (annealing
step?). The measurements 4.2.1 to 4.2.3 are then repeated with the following
special conditions:
-
the detector is kept at -10°C throughout the
measurement procedure
-
the CV measurement trace frequency should be 100Hz
Acceptance
Maximum operating voltage of 350V
maximum current (guard and bias) <1mA at -10°C
and 350V
Number of bad strips should remain within criteria
of 4.2.3
4.2.6 Interstrip Capacitance
Aim
To ensure the interstrip capacitance is within specifications.
Procedure
Place the detector on the chuck of a probestation,
and contact the bias rail by probe needle. Contact three adjacent metal
strips (pad row C) with probe needles. Measure the capacitance between
the central strip and its neighbours on both sides as a function of detector
bias up to 150V. Use 100 kHz test frequency with CR in parallel.
Acceptance
Interstrip capacitance < 1.0 pF/cm at 150V bias.
4.2.7 Polysilicon Bias Resistance and Interstrip
Resistance
Aim
Determine the bias resistor value is within specificatons
and that the interstrip isolation is sufficient when under bias.
Procedure
This measurement yields both the polysilicon bias
resistance and the interstrip resistance. Place the detector backplane
on the chuck of a probestation and contact the bias rail and a strip implant
by probe needles. Ground the bias rail and apply bias to the backplane.
Use either an ohmmeter or perform an IV to determine the resistance between
the strip implant and bias rail as a function of bias voltage (increase
detector bias from 0 V to 5 V in steps of 0.2 V).
Acceptance
Interstrip resistance is sufficient if the measured
resistance vs detector bias plateaus. The plateau level resistance is equivalent
to the polysilicon bias resistance, and must be within 1.25 +/- 0.75 Mohm.
Daves original includes a test for resistor
contact here; I omit this, hoping it can be caught under the variation
described under the strip integrity tests.
4.2.8 Coupling capacitance
Aim
To determine the coupling capacitance between the
strip metal and strip implant, to check that the value is within specification
and to monitor processing consistency.
Procedure
Place the detector backplane on the chuck of a probestation
and contact the metal and implant of a strip with probe needles. Measure
the capacitance between the metal and implant at 1 kHz with CR in PARALLEL.
Acceptance
Coupling capacitance > 20 pF/cm
4.3 Additional Test structure tests
A batch of test structures should pass all of the
following tests before being accepted
4.3.1 Metal Series resistance
Aim
Measurement of detector metal strip series resistance
on a representative test structure
Procedure
Apply an ohmmeter to the test structure, probed on
a probe station
Acceptance
Resistance<15*/cm
4.3.2 Polysilicon bias resistance
Aim
Measurement of detector bias resistors on a representative
test structure
Procedure
Apply an ohmmeter to the probed test structure
Acceptance
Resistance =1.5M* ± 0.5M*
4.3.3 Sheet resistance of implants
Aim
Measurement of sheet resistance of implant, p or
n
Procedure
Apply ohmmeter to representative test structure
Acceptance
Sheet resistance<200k*/cm
4.3.4 Flat-band voltage
Aim
Measurement of flat band voltage of representative
MOS structure
Procedure
Place the MOS on a probestation chuck and contact
the MOS with a probe needle. Measure capacitance across the MOS (at 1kHz
with CR in SERIES) as a function of bias up to 50V.
Acceptance
There is no defined acceptance criteria. Flat band
voltage is used as a monitor of processingconsistency.
4.4 Fan-in tests
4.x Other tests, metrology
5. Table of tests, variables stored and acceptance criteria
(numbers are for each module; tests during production)
| Piece under test |
#these pieces |
Test description |
Reference |
Variable |
#variables
per piece |
Nominal value |
Acceptable range |
| Detector |
4 |
Detector IV |
IV curves |
Current @ 150V |
1 |
? |
<6µA |
|
|
Detector IV |
|
Current @ 300V |
1 |
? |
<20µA |
|
|
Visual inspection |
|
Visible defects |
text/boolean |
None |
|
|
|
Strip integrity |
|
Neighbour shorts |
1 list |
None |
<14 |
|
|
Strip integrity |
|
Punchthrough |
1 list |
None |
<14 |
|
|
Strip integrity |
|
Discontinuity |
1 list |
None |
<14 |
|
|
Strip integrity |
|
Total # defects |
1 |
None |
<14 |
|
|
|
|
|
|
|
|
| Fanin |
2 |
Visual inspection |
|
Visible defects |
text/boolean |
None |
<1% |
|
|
|
|
Electrical defects |
1 list |
None |
<1% |
| Hybrid |
2 |
Visual inspection |
|
Visible defects |
text/boolean |
None |
None |
|
|
Current check |
|
Vdd current |
1 |
40mA |
±20% |
|
|
|
|
Vcc current |
1 |
44mA |
±20% |
|
|
Current after burnin |
|
Vdd current |
1 |
40mA |
|
|
|
|
|
Vcc current |
1 |
44mA |
|
|
|
Full test vector run 2.1.3(4) |
Full test vector |
Full compliance |
boolean |
OK |
OK |
|
|
Data run 2.1.3(5) |
|
Thresholds |
6*128 |
? |
|
|
|
|
|
Gains |
6*128 |
? |
|
|
|
|
|
Noise |
6*128 |
? |
|
|
|
|
|
Strobe delays |
6 |
? |
|
|
|
|
|
Threshold spread |
1 |
|
|
|
|
|
|
average gain |
1 |
|
|
|
|
|
|
gain spread |
1 |
|
|
|
|
|
|
average noise |
1 |
|
|
|
|
|
|
optimal DAC settings |
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
6. Infrastructure requirements
6.1 Basic requirements
It is assumed that the tests are carried out in a
lab with access to standard electronics test equipment (oscilloscopes,
multimeters etc.) In addition, a microscope with up to x80 magnification
is assumed to be available for various visual inspections.
6.2 Assembled hybrid testing
Tests described in 2.1.3, and section 4.1.
Equipment
Environment chamber or test box, enabling temperature
cycling from -20 to +50 deg C with humidity control (or nitrogen flushing)
to prevent condensation.
Burn in and other tests are to be performed in
parallel, so (at least!)two sets of the following are required:
-
Low voltage power supplies with current limit and
current display
-
VME crate with: DSP unit, or SEQSI and DRAFT, or
ROD
-
VME controller: VME processor or PCI-VME interface
to a PC
-
Database software
6.3 Detector testing
Described in section 4.2
Equipment
-
Manual prober
-
Automatic or semi-automatic probestation
-
High (>500V) voltage source, >1mA compliance
-
Picoammeter
-
LCR meter, with blocking box for HV application and
frequency range 100Hz to 100kHz
-
Ohmmeter
-
Temperature+humidity monitor
-
Environment chamber or cooled measurement box with
humidity control
-
Switching matrix for stability measurements
-
Bonding machine
-
PC with GPIB controller and suitable instrument control
software
-
Database software
-
Suitable dry storage
6.4 Module tests
Described in section 2.3
Equipment
-
HV power supply, >500V, >1mA
-
Picoammeter
-
Environment chamber or test box allowing cycling
+20 to -20
-
Hybrid test equipment as in section 6.2
-
Thermal imaging system or precise pyrometer
-
Light injection system or source/scintillator set
up
-
Metrology table
-
Suitable dry storage
-
Database software
6.5 Other component tests
Metrology....?