//_____________________________________________________________________________ // Plug strip d-bank analysis module: below are the examples of what // one can do in the interactive session // // PrintLevel: // // 1: print CES data for all the events // 101: print events with at least one channel with ADC counts in [50,55] //_____________________________________________________________________________ /* ****** to run: (note naming convention: class_name = "T"+module_name+"Module"), the source code of the class is stored in TStnAna x("results/ar0192ea.0001cmu0.stn_new"); TStnAna x("results/dataval_muon.root"); .L TCesAnaModule.cc+ x.AddModule(new TCesAnaModule); x.Run(); ****** to display a histogram TCesAnaModule::Hist_t* c; TCesAnaModule* m = (TCesAnaModule*) x.GetModule("CesAna"); c = m->GetHist(); c->fAdcCounts->Draw(); ****** to process one event (#11 in the ntuple) and to print the data x.ProcessEvent(11) TCesAnaModule* m = (TCesAnaModule*) x.GetModule("CesAna"); TCesDataBlock* ces = m->GetCesDataBlock(); TStnHeaderBlock* hdr = m->GetHeaderBlock (); ces->Print(); hdr->Print(); */ #include "TROOT.h" #include "TSystem.h" #include "TF1.h" #include "TCanvas.h" #include "Stntuple/obj/TStnHeaderBlock.hh" #include "Stntuple/obj/TStnTrackBlock.hh" #include "TCesAnaModule.hh" // ClassImp(TCesAnaModule) //_____________________________________________________________________________ TCesAnaModule::TCesAnaModule(const char* name, const char* title): TStnModule(name,title) { } //_____________________________________________________________________________ TCesAnaModule::~TCesAnaModule() { } //_____________________________________________________________________________ void TCesAnaModule::BookHistograms() { char name [200]; char title[200]; // delete old histograms Delete("hist"); // book histograms sprintf(name, "%s_adc_counts",GetName()); sprintf(title,"%s: CES: ADC spectrum ",GetName()); fHist.fAdcCounts= new TH1F(name, title,500 ,0,500); AddHistogram(fHist.fAdcCounts); for (int side=0; side<2; side++) { for (int iw=0; iw<24; iw++) { sprintf(name, "%s_strip_ped_%1i_%2i",GetName(),side,iw); sprintf(title,"%s: CES: strip ADCs side=%i wedge=%i",GetName(),side,iw); fHist.fStripPed[side][iw] = new TH1F(name, title,128 ,0,128); AddHistogram(fHist.fStripPed[side][iw]); sprintf(name, "%s_wire_ped_%1i_%2i",GetName(),side,iw); sprintf(title,"%s: CES: wire ADCs side=%i wedge=%i",GetName(),side,iw); fHist.fWirePed[side][iw] = new TH1F(name, title,64,0,64); AddHistogram(fHist.fWirePed[side][iw]); } } int k =0; for (int iw=14; iw<16; iw++) { sprintf(name, "%s_strip_profile_%2i",GetName(),iw); sprintf(title,"%s: CES(WEST): strip profile wedge=%i",GetName(),iw); fHist.fStripProfile[k] = new TH1F(name, title,128,0,128); AddHistogram(fHist.fStripProfile[k]); fHist.fStripProfile[k]->SetMinimum(0); fHist.fStripProfile[k]->SetMaximum(300); sprintf(name, "%s_wire_profile_%2i",GetName(),iw); sprintf(title,"%s: CES(WEST): wire profile wedge=%i",GetName(),iw); fHist.fWireProfile[k] = new TH1F(name, title,64,0,64); AddHistogram(fHist.fWireProfile[k]); fHist.fWireProfile[k]->SetMinimum(0); fHist.fWireProfile[k]->SetMaximum(300); k++; } } //_____________________________________________________________________________ int TCesAnaModule::BeginJob() { // register the data blocks and book the histograms RegisterDataBlock("CesDataBlock","TCesDataBlock",&fCesDataBlock); BookHistograms(); //----------------------------------------------------------------------------- // handle print level //----------------------------------------------------------------------------- const char* env; env = gSystem->Getenv(Form("%s_PrintLevel",GetName())); if (env) { fPrintLevel = atoi(env); printf(" %s: fPrintLevel = %i\n",GetName(),fPrintLevel); } return 0; } //_____________________________________________________________________________ int TCesAnaModule::BeginRun() { return 0; } //_____________________________________________________________________________ int TCesAnaModule::Event(int ientry) { fCesDataBlock->GetEntry(ientry); // do whatever you want if (PrintLevel() == 1) { GetHeaderBlock()->Print(); fCesDataBlock->Print(); } int print_101 = 0; for (int is=0; is<2; is++) { for (int iw=0; iw<24; iw++) { if (fCesDataBlock->GetNHitStrips(is,iw) > 0) { // there is something in this data block for (int ich=0; ich<128; ich++) { int adc_counts = fCesDataBlock->GetStripData(is,iw,ich); fHist.fAdcCounts->Fill(adc_counts); fHist.fStripPed[is][iw]->Fill(adc_counts); if ((PrintLevel() == 101) && (adc_counts < 50)) { printf(" is, iw, adc_counts = %2i %2i %10i\n",is,iw,adc_counts); print_101 = 1; } } } if (fCesDataBlock->GetNHitWires(is,iw) > 0) { // there is something in this data block for (int ich=0; ich<64; ich++) { int adc_counts = fCesDataBlock->GetWireData(is,iw,ich); fHist.fAdcCounts->Fill(adc_counts); fHist.fWirePed[is][iw]->Fill(adc_counts); } } // event-by-event histograms if (is == 0) { if ( (iw == 14) || (iw == 15)) { int k = (iw-14); fHist.fStripProfile[k]->Reset(); fHist.fWireProfile[k]->Reset(); for (int ich=0; ich<128; ich++) { int adc_counts = fCesDataBlock->GetStripData(is,iw,ich); fHist.fStripProfile[k]->SetBinContent(ich+1,adc_counts); } for (int ich=0; ich<64; ich++) { int adc_counts = fCesDataBlock->GetWireData(is,iw,ich); fHist.fWireProfile[k]->SetBinContent(ich+1,adc_counts); } } } } } if (print_101) GetHeaderBlock()->Print("ADC counts in 50-55 range\n"); return 0; } //_____________________________________________________________________________ void TCesAnaModule::DisplayEvent() { char name[] = "TCesAnaModule_DisplayEvent_canvas"; char title[] = "West plug CES events"; TCanvas* c = (TCanvas*) gROOT->FindObject(name); if (! c) { c = new TCanvas(name, title,0,0,800,600); c->Divide(2,2); } for (int k=0; k<2; k++) { c->cd(2*k+1); fHist.fStripProfile[k]->Draw(); c->cd(2*k+2); fHist.fWireProfile[k]->Draw(); } c->Modified(); c->Update(); } //_____________________________________________________________________________ int TCesAnaModule::EndJob() { printf("----- end job: ---- %s\n",GetName()); return 0; }